Multi-port, gigabit serdes transceiver capable of automatic fail switchover

ABSTRACT

A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the transceiver can connect any of the serial ports to another serial port or to a parallel port. The transceiver further includes a switch, a logic core, and a bus. The switch is selectively coupled to at least a first port and a second port. The switch activates the first port and deactivates the second port based on satisfaction of a condition associated with the first port. The logic core operates the serial and parallel ports, and the bus connects the ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the ports. The ring structure provides efficient communication between the logic core and the ports.

CROSS-REFERENCED TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent applicationSer. No. 10/694,788, filed on Oct. 29, 2003, now U.S. Pat. No.7,035,228, which claims the benefit of U.S. Provisional Application No.60/421,780, filed on Oct. 29, 2002, both of which are incorporatedherein by reference in their entireties.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to serializer/deserializerintegrated circuits with multiple high speed data ports, and moreparticularly to a serial and de-serializer chip that includes thefunctionality to switch between multiple high speed data ports.

2. Background Art

High speed data links transmit data from one location to another overtransmission lines. These data links can include serializer data linksthat receive data in a parallel format and convert the data to a serialformat for high speed transmission and deserializer data links thatreceive data in serial format and convert the data to a parallel format.Data links that include serializer and deserializer functionality arereferred to as serializer/deserializer data links (i.e., SERDES). SERDESdata links can be part of a backplane in a communications system (e.g.,Tyco Backplane 30-inch trace).

In a high speed back plane configuration, it is often desirable toswitch between multiple Serdes links. In other words, it is oftendesirable to switch between any one of multiple Serdes links to anotherSerdes link, and to do so in a low power configuration on a singleintegrated circuit.

BRIEF SUMMARY OF THE INVENTION

A multi-port Serdes transceiver includes multiple parallel ports andserial ports, and includes the flexibility to connect any one of theparallel ports to another parallel port or to a serial port, or both.Furthermore, the multi-port transceiver chip can connect any one of theserial ports to another serial port or to one of the parallel ports. Themulti-port Serdes transceiver is able to operate at multiple data rates.

The Serdes transceiver includes configuration logic that is capable ofactivating and/or deactivating ports in the transceiver. Theconfiguration logic can detect that a first port is active and determinewhether to deactivate the first port based on whether a failure isdetected. If the first port is deactivated, a second port is activatedto take over operations associated with the first port. Specificfunctions can be deactivated with respect to a port. For example,transmitting functions of a port can be deactivated while the receivingfunctions remain activated, or vice versa.

The multi-port Serdes transceiver also includes a packet bit error ratetester (BERT). The packet BERT generates and processes packet test datathat can be transmitted over any of the serial ports to perform biterror testing. The packet BERT can monitor (or “snoop”) between theserial ports. In other words, if data is being transmitted from oneserial port to another serial port, the packet BERT can capture andstore a portion of this data for bit error testing.

The substrate layout of the multi-port Serdes transceiver chip isconfigured so that the parallel ports and the serial ports are on theouter perimeter of the substrate. A logic core is at the center of thesubstrate, where the logic core operates the serial and parallel dataports, and a bus that connects the data ports. The bus can be describedas a “ring” structure (or donut “structure”) around the logic core, andis configured between the logic core and the data ports. The ringstructure of the bus provides efficient communication between the logiccore and the various data ports.

The Serdes transceiver described herein is highly flexible and can beconfigured to provide multiple different transceiver products fromenabling and disabling various serial and parallel data ports. This isaccomplished using a configuration logic circuit that enables/disablesthese data ports. As a result, several different transceiver products,with different capabilities and price points, can be configured from asingle semiconductor die.

Further features and advantages of the present invention, as well as thestructure and operation of various embodiments of the present invention,are described in detail below with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is described with reference to the accompanyingdrawings. In the drawings, like reference numbers indicate identical orfunctionally similar elements. Additionally, the left-most digit(s) of areference number identifies the drawing in which the reference numberfirst appears.

FIG. 1 illustrates a multi-port Serdes chip according to embodiments ofthe present invention.

FIG. 2 further illustrates the multi-port Serdes chip including aparallel-to-serial conversion according to embodiments of the presentinvention.

FIG. 3 further illustrates the operation of the transceiver 100 in therouting of serial data between ports according to embodiments of thepresent invention.

FIG. 4 illustrates a multi-port Serdes transceiver 400, which is oneembodiment of the transceiver 100.

FIG. 5 illustrates a substrate layout of the multi-port Serdestransceiver chip according to embodiments of the present invention.

FIG. 6 illustrates a section of the bus 106 according to embodiments ofthe present invention.

FIG. 7 further illustrates the bus 106 having equal length transmissionlines according to embodiments of the present invention.

FIG. 8 illustrates a transceiver 800, which one configuration of thetransceiver 400.

FIG. 9 illustrates a transceiver 900, which is another configuration ofthe transceiver 400.

FIG. 10 illustrates a transceiver 1000, which is another configurationof the transceiver 400.

FIG. 11 illustrates a transceiver 1100, which is another configurationof the transceiver 400.

FIG. 12 illustrates a transceiver 1200, which is another configurationof the transceiver 400.

FIG. 13 illustrates a communications system with a backplane interface.

FIG. 14 illustrates a transceiver 1400 with automatic polarity swapaccording to embodiments of the present invention.

FIG. 15 illustrates a flowchart that further describes automaticpolarity swap according to embodiments of the present invention.

FIG. 16 illustrates a system utilizing automatic fail switchoveraccording to an embodiment of the present invention.

FIG. 17 illustrates the system of FIG. 16 according to anotherembodiment of the present invention.

FIG. 18 illustrates the system of FIG. 17 including switches having afirst configuration according to an embodiment of the present invention.

FIG. 19 illustrates the system of FIG. 17 including switches having asecond configuration according to an embodiment of the presentinvention.

FIG. 20 illustrates the system of FIG. 17 including switches having athird configuration according to an embodiment of the present invention.

FIG. 21 illustrates the system of FIG. 17 including switches having afourth configuration according to an embodiment of the presentinvention.

FIG. 22 illustrates the system of FIG. 16 according to yet anotherembodiment of the present invention.

FIG. 23 is a flow chart of a method of performing automatic failswitchover according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a multi-port transceiver 100 according to embodimentsof the present invention. Transceiver 100 includes a plurality of serialports 104 a-d, a plurality of parallel ports 102 a-b, and a bus 106.Each of the plurality of serial ports 104 is capable of transmitting andreceiving data in a serial format, and each of the parallel ports 102 iscapable of transmitting and receiving data in a parallel format. Forexample, the serial ports 104 could be transmitting and receiving serialdata with corresponding switches (e.g. MACs) 108 a-d.

The transceiver 100 also includes a bus 106 that is coupled to theserial ports 104 a-d and the parallel ports 102 a and 102 b. The bus 106enables any serial port 104 to be connected to any other serial port 104and to any parallel port 102 for data transmission, and vice versa.Therefore, data can be transmitted from any switch 108 to any otherswitch 108, or can be transmitted and received to and from the parallelports 102. For example, data received at the serial port 104 a fromswitch 108 a can be routed to the serial port 104 c by the bus 106, fortransmission to the switch 108 c. Additionally, data from the switch 108a can be routed to the other serial ports 104 b-d and to the parallelports 102 a and 102 b through the bus 106.

FIG. 2 illustrates that each serial port 104 can include aserial-to-parallel converter 202, so that serial data processed by theport 104 can be converted to parallel data, and vice versa. In otherwords, serial data received by serial ports 104 from correspondingswitches 108 can be converted to parallel data and routed on the bus106. The serial-to-parallel converters 202 are bi-directional, so thatparallel data from the bus 106 can be converted to serial data fortransmission from the serial port 104 to the corresponding switch 108.Furthermore, the parallel data from the bus 106 can also be converted toserial for transmission to the switch 108.

FIG. 2 also illustrates the bus 106 to have a “ring structure” thatenables the data to be sent from one adjacent port 104 to anotheradjacent port 104. For example, data from port 104 a is directlytransmitted to ports 104 b and 104 c over the ring structure of the bus106. Therefore, data from any one port 104 can be connected to anotherport 104 using the bus 106 by transmitting data around the ringstructure of the bus from one port 104 to another port 104. Furthermore,the bus 106 transmits data in a parallel format since it is connected tothe parallel side of the serial to parallel converters 202. The parallelformat of the bus 106 enables parallel data to be tapped out from thebus 106 at the parallel ports 102 a and 102 b. The ring structure of thebus 106 will be further described herein.

FIG. 3 illustrates a flowchart 300 that further describes the operationof the transceiver 100 in the routing of serial data between ports. Instep 302, serial data is received at a first serial port 104, from aswitch 108 for example. In step 304, the serial data is converted toparallel data. In step 306, the parallel data is routed from oneadjacent port 104 to another via the bus 106 until a destination port104 is reached. In step 308, the parallel data is converted back toserial. In step 310, the serial data is transmitted from the serialdestination port 104, to a destination switch 108 for example.

The ports of the transceiver 100 can be configured to operate over anumber of different data standards, as will be described further herein.For example, the serial ports 104 can transmit data to the switches 108according to an XAUI serial protocol. The XAUI serial data is convertedto XGMII parallel data for transmission over the parallel bus 106, andtherefore the XGMII parallel data can be tapped-out by the parallelports 102 a and 102 b.

Furthermore, the inverse operation can also be performed. Parallel datais received at a parallel port 102 and routed to the other parallel port102 or routed to a serial destination port 104. If routed to a serialdestination port, then the data is serialized prior to transmission.

FIG. 4 illustrates a multi-port Serdes transceiver 400, which is oneembodiment of the transceiver 100. The Serdes transceiver 400 includesmultiple parallel ports 102 and serial ports 104, and includes theflexibility to connect any one of the parallel ports 102 to anotherparallel port 102 or to a serial port 104, or both. Furthermore, themultiport transceiver chip 400 can connect any one of the serial ports104 to another serial port 104 or to one of the parallel ports 102.

More specifically, the Serdes transceiver chip 400 includes two paralleltransceiver ports 102 a,b, and four serial transceiver ports 104 a-d.However, the invention is not limited to the number of ports shown.Other configurations having a different number of ports could be used.The parallel transceiver ports 102 a,b transmit and receive data in aparallel format. The parallel transceiver ports 102 a,b can be XGMIIparallel ports, for example, where the XGMII transceiver protocol isknown to those skilled in the arts. Each XGMII port 102 can include 74data pins, for example, operating at 1/10 the data rate of the serialports 104. For example, the 74 pins can transmit 36 data signals andreceive 36 data signals, simultaneously, and 2 clock signals (1 transmitand 1 receive).

The four serial ports 104 a-d can be XAUI serial ports, and transmit andreceive data in a serial format. Each serial port 104 can be a quadserial port having four serial differential data lines using the XAUIprotocol that is known to those skilled in the arts. In embodiments ofthe invention, the serial ports 104 can operate at data rates of 3.125GHz, 2.5 GHz, and 1.25 GHz. In other words, the transceiver chip 100 isa mult-rate device. However, the XAUI data rates above are effectivelyquadrupled since there are four serial data lines in each serial port104. Therefore, the 2.5 GHz data rate is equalvalent to a 10 GHz datarate. As discussed above, the parallel data rates can operate at 1/10 ofthe data rates of the serial data.

The serial ports 104 can be further described as 10 Gigabit extensionsub-letter (XGXS). In other words, XGXS defines the parallel-to-serialconversion between the parallel XGMII protocol to serial XAUI protocol,according to the IEEE Std 802.3ae, the entire standard of which isincorporated herein by reference. The serial ports 104 receive serialXAUI data and convert it to parallel XGMII data according the XGXSprotocol. The parallel XGMII data is routed from adjacent port toadjacent port on the parallel bus 106.

As discussed above, the parallel ports 102 and the serial ports 104 arelinked together by the parallel bus 106. The parallel bus 106 enablesdata to travel between all the ports 102 and 104. More specifically thebus 106 enables data to travel from one parallel port 102 to anotherparallel port 102, and to travel from one parallel port 102 to a serialport 104. Multiplexers 402 connect the bus 106 to the parallel ports 102and to the serial ports 104. The serial port 104 performs a parallel toserial conversion when receiving parallel data that is to be sent outserial. Likewise the bus 106 enables data to travel from one serial port104 to another serial port 104, and to travel between a serial port 104and a parallel port 102. The parallel port 102 enables parallel data tobe tapped from the parallel bus 106 so that parallel data (e.g. XGMIIdata) can be transmitted from the transceiver 400. The multi-port Serdestransceiver 400 is highly flexible in being able to connect multipleparallel ports 102 to multiple serial ports 104, and vice versa.

In embodiments, the Serdes transceiver chip 400 can be implemented on asingle CMOS substrate. For example, the Serdes transceiver chip 400 canbe implemented using a low power 0.13-micron CMOS process technology,which lends itself to higher levels of integration and application.

The transceiver 400 enables dual unit operation, where one parallel port102 is paired up with two of the serial ports 104 and the other parallelport 102 is paired up with the other two serial ports 104. For example,parallel port 102 a can be paired with serial ports 104 a and 104 b.Likewise, the parallel port 102 b can be paired with serial ports 104 cand 104 d. However, there is complete selectivity of the ports that aregrouped together for dual unit operation. For example, parallel port 102a can be paired with either serial ports 104 a and 104 b, or serialports 104 c and 104 d. In a backplane configuration, this providesflexibility to connect a parallel port to one or more serial ports, andwith redundancy.

The transceiver 400 also includes a packet bit error rate tester (BERT)406. The packet BERT 406 generates and processes packet test data thatcan be transmitted over any of the serial ports 104 to perform bit errortesting. Any type of packet data can be generated to perform the testingand at different data rates. For example, the packet BERT 406 cangenerate packet data that can be used to test the Serdes data link. Assuch, the packet BERT 406 provides a built-in self test for the Serdesdata link. The packet BERT 406 generates test data that is sent over oneor more of the serial ports 104 using the bus 106 to perform the biterror rate testing of the Serdes data link. For example, the packet BERT406 can generate test data for a data link formed by enabling the serialports 104 a and 104 b to connect the switch 108 a to the switch 108 c.Likewise, the packet BERT 406 can capture test data received over anyone of the serial ports 104 or parallel ports 102 using the bus 106 forcomparison with test data that was sent out. A bit error rate can thenbe determined based on this comparison.

In one embodiment, the packet BERT 406 is RAM-based so that the testdata is stored and compared in a RAM memory to perform the bit errorrate test. In another embodiment, the packet BERT 406 is logic based sothat the test data is generated by a logic function, and transmittedacross a Serdes link. Upon receipt back, the test data is re-generatedby the logic packet BERT 406, for comparison with the original test datathat was sent over the Serdes data link. A RAM packet BERT 406 is moreflexible than a logic packet BERT 406 because there is no limitation onthe data that can be stored in the RAM packet BERT 406. However, a logicpacket BERT 406 is more efficient in terms of substrate area because aRAM occupies more area than a logic circuit.

Since the packet BERT 406 shares the same bus 106 with the serial ports104, the packet BERT 406 can monitor (or “snoop”) between the serialports 104. In other words, if data is being transmitted from one serialport 104 to another serial port 104, the packet BERT 406 can capture andstore a portion of this data for bit error testing. In one embodiment,the packet BERT 406 “blindly” captures data being sent from one serialport 104 to another serial port 104. In another embodiment, the packetBERT 406 starts capturing data after a particular byte of data istransmitted. In another embodiment, the packet BERT 406 starts capturingdata after an error event occurs. The packet BERT 406 is furtherdescribed in U.S. patent application Ser. No. 10/681,244, filed on Oct.9, 2003, which is incorporated by reference herein in its entirety.

The Serdes transceiver chip 400 also includes the ability to includeother optional logic blocks 408 that are not necessary for the operationof the Serdes transceiver. In other words, the logic blocks 408 could becustomer driven logic blocks or some other type of logic block. Theseoptional logic blocks 408 can transmit and receive data over the serialports 104 or parallel ports 102 using the bus 106. The packet BERT 406and the optional blocks 408 connect to the bus 106 using themultiplexers 404.

The Serdes transceiver chip 400 also includes a management interface 412that enables the configuration of the portions (parallel ports 102,series port 104, packet BERT 406, and optional logic blocks 408) of thetransceiver chip 100. The management interface 412 includes two pads 414that enable two different management chips to program and control theportions of the transceiver chip 400 using MDIOs blocks 416. Forexample, one management chip connected to pad 414 a could control theparallel port 102 a and the serial ports 104 a and 104 b, and anothermanagement chip connected to pad 414 b could control the parallel port102 b and the serial ports 104 c and 104 d. The management interface 412is configured to be compatible with both IEEE Std. 802.3 clause 45 andthe IEEE Std. 802.3 clause 22 management standards. In other words, onemanagement pad 414 a and MDIO block 416 a can be programmed to beresponsive to clause 45 electricals and protocol, and the othermanagement pad 414 b and MDIO block 416 b could be responsive to clause22 electricals and protocol. Furthermore, the management pads 414 andMDIO blocks can mix and match clause 22 and clause 45 electrical andprotocols. For example, management pad 414 a and MDIO block 416 a can beresponsive to clause 22 electricals and clause 45 protocols, and viceversa. Similar mix and match can be done for the management pad 414 band the MDIO block 416 b. The management data pads are further describedin U.S. patent application Ser. No. 10/694,729, titled “Multipurpose andIntegrated Pad Ring for Integrated Circuit”, filed Oct. 29, 2003, andU.S. patent application Ser. No. 10/694,730, titled “ProgrammableManagement I/O Pads for an Integrated Circuit”, filed Oct. 29, 2003,both of which are incorporated by reference herein in its entirety.

FIG. 5 illustrates the substrate layout 500 for the Serdes transceiver400 according to embodiments of the invention. The substrate layout 500is configured to minimize the substrate area of the transceiver 400, andefficiently provide the port interconnections described above.

The substrate layout 500 is configured so that the parallel ports 102a,b and the serial ports 104 a-d are on the outer perimeter of thesubstrate 200, as shown. In other words, the serial ports 104 a and 104b are on a first side of the substrate layout 500 and the serial ports104 c and 104 d are on a second side of the substrate layout 500. Theparallel port 102 a is on a third side of the substrate layout 500. Andthe parallel port 102 b is on a fourth side of the substrate layout 500.A logic core 502 is at the center of the substrate 500, where the logiccore 502 operates the bus 106 and the serial 104 and parallel 102 dataports. The management interface 412, the packet BERT 406, and theoptional logic blocks 408 a-c are adjacent to the logic core 502 asshown. The bus 106 can be described as a “ring” structure (or donut“structure”) around the logic core 502, and is placed in between thelogic core 502 and the data ports 102 and 104 that occupy the parameterof the substrate layout 500. Furthermore, the ring structure of the bus106 also provides efficient communication between the logic core 502 andthe various data ports 102 and 104. Furthermore, the ring structure ofthe bus 106 also provides efficient communication between the managementinterface 412, the packet BERT 406, the optional logic blocks 408, andthe various data ports 102 and 104.

The bus 106 is illustrated as 8 sections 106 a-106 g for ease ofillustration. Each section provides an interface to the respective dataports 102 or 104 that are adjacent to the respective sections.

FIG. 6 represents one of the 8 sections 106 a-106 g of the bus 106according to embodiments of the present invention. Each section of thebus 106 can be represented as two paths 608 and 610. Data enters the bus106 through a buffer 602 and proceeds to its destination along the path608 and through the buffers 604. Data passes from one section to anothersection of the bus 106 using the path 610 and passing through thebuffers 612. The mux 606 represents data passing from the bus 106 to afunctional block, such as a data port 102, 104 or the packet BERT 406.The actual wires and buffers on the bus 106 are matched to minimizesignal distortion.

In embodiments, the data wires in the bus 106 are deposited on thesubstrate 500 in a particular fashion. Namely, a power or ground isplaced between adjacent (or near by) data wires. Furthermore, adjacentdata wires on the bus 106 are placed on two separate layers. Therefore,a power or ground will be above or below a data wire, and adjacent to adata wire. Therefore, two nearby data wires will not be located directlyadjacent one another, but instead will be positioned diagonal to eachother, thereby reducing cross talk.

The parallel bus 106 is further described in U.S. patent applicationSer. No. 10/695,458, titled “Cross Link Multiplexer Bus”, filed Oct. 29,2003, and incorporated by reference herein in its entirety.

The multi-port Serdes transceiver 400 supports multiple different dataprotocols at the pads including XGMII, TBI, RTBI, HSTL, SSTL, or LVTTLprotocols, and others.

FIG. 7 further illustrates an example layout of the bus 106. The wires702 between data ports 102, 104 are configured to have the same pathlengths so as to minimize signal distortion. In other words, wires 702a-d are deposited so as to have the same path length so as to reducesignal distortion.

The multi-port Serdes transceiver 400 includes the ability to change thetiming of the data ports 102 and 104. This includes the ability tochange the timing between the data and clock signals. In other words,the registers in the data ports 102 and 104 can be re-programmed tooperate at different timing protocols.

The Serdes transceiver 400 is highly flexible and can be configured toprovide multiple different transceivers by enabling and disablingvarious serial and parallel data ports. This is accomplished using aconfiguration logic circuit 418 that controls the registers and timingof the data ports 102 and 104, and also enables/disables these dataports. As a result, several different transceiver products can beconfigured from a single semiconductor die that is manufactured with the4 serial data ports and 2 parallel data ports. For instance, FIG. 1illustrates an embodiment, where all four serial ports 104 and bothparallel ports 102 are enabled and accessible to exchange data. Thetransceiver 400 represents the maximum capability that can be achievedfrom the 4 serial and two parallel data ports. Other specific examplesare discussed below, but the invention is not limited to these examples.

FIG. 8 illustrates a transceiver 800 having 4 serial XGXS data ports104. The two parallel ports 102 have been disabled using configurationlogic 418 and/or by not bonding the parallel ports to the output pins ofthe semiconductor package. The transceiver 800 enables a first physicallayer device 810 a (e.g., a backplane or a laser module) to exchangedata with a second physical layer device 810 b.

FIG. 9 illustrates a transceiver 900 having 2 serial XGXS data ports 104a and 104 b and two XGMII parallel data ports 102 a and 102 b. The othertwo serial data ports 104 c and 104 d have been disabled usingconfiguration logic 418 and/or by not bonding the ports to the outputpins of the semiconductor package. The transceiver 900 enables theswitch 108 a to exchange data with the switch 108 b, and allows theparallel XGMII data to be tapped from the parallel bus 106 using theparallel XGMII data ports 102 a 102 b.

In another embodiment of FIG. 9, the timing of the serial and parallelports is varied to provide another transceiver product. For instance,the two XGXS serial ports can be configured as 8 Serdes ports thatoperate at a slower data rate than the XGXS data ports. Likewise, thetwo XGMII parallel data ports can be configured as 8 TBI data ports thatalso operate at a slower data rate. In general, the timing of the dataports can be revised and reconfigured for each of the transceiverconfigurations shown herein.

FIG. 10 illustrates a transceiver 1000 having 2 serial XGXS data ports104 a and 104 b and only one XGMII parallel data port 102 a. The othertwo serial data ports 104 c and 104 d and the parallel port 102 b havebeen disabled using configuration logic 418 and/or by not bonding theports to the output pins of the semiconductor package. The transceiver1000 enables data to be exchanged between serial data ports 104 c and104 d, and allows the parallel XGMII data to be tapped from the parallelbus 106 using the parallel XGMII data port 102 a.

FIG. 11 illustrates a transceiver 1100 having 2 serial XGXS data ports104 a and 104 c and no XGMII parallel data port 102 a. The other twoserial data ports 104 c and 104 d and the parallel ports 102 have beendisabled using configuration logic 418 and/or by not bonding thedisabled ports to the output pins of the semiconductor package. Thetransceiver 1100 enables data to be exchanged between serial data ports104 a and 104 c.

FIG. 12 illustrates a transceiver 1200 having 3 serial XGXS data ports104 a, 104 b, and 104 d and one XGMII parallel data port 102 a. Theother serial data ports 104 c and the parallel port 102 a have beendisabled using configuration logic 418 and/or by not bonding thedisabled ports to the output pins of the semiconductor package. Thetransceiver 1200 enables data to be exchanged between serial data ports104 a, 104 b, and 104 d.

Based on the above discussion, it is apparent that the base transceiver400 is highly flexible and enables multiple transceiver products, withdifferent capabilities and price points, to be configured and sold fromthe base semiconductor die.

Automatic Polarity Swap

FIG. 13 illustrates a communications system 1300 having a first Serdestransceiver 100 a that communicates data with a second Serdestransceiver 100 b through an interface 1303, that may be a backplane forexample. The Serdes transceivers 100 a and 100 b can be any type of thetransceivers discussed herein, or any other type of transceiver. TheSerdes transceiver 100 a can be represented as having a differentialinput 1301 p and 1301 n and a differential output 1302 p and 1302 n.Likewise, the Serdes transceiver 100 b can be described as having adifferential input 1304 p and 1304 n, and a differential output 1306 pand 1306 n.

During the configuration of the backplane 1303, the differential output1302 of the transceiver 100 a can be mistakenly cross-connected with thedifferential input 1304 of the Serdes transceiver 100 b. In other words,the 1302 n output of the transceiver 100 a can be mistakenly connectedto the 1304 p input of the transceiver 10 b. Likewise, the 1302 p outputof the transceiver 100 a can be mistaken connected to the 1304 n inputof the transceiver 100 a. The result of such a cross-connection is thatinvalid data words are received at the Serdes transceiver 100 b, whichcauses an increase in the bit error rate (BER).

FIG. 14 illustrates an apparatus and method of automatic polarity swapto address the cross-connection problem discussed with reference to FIG.13. FIG. 14 illustrates a transceiver 1400 having an error check andcorrection module 1401. The error check and correction module 1401includes an error check 1402 and a exclusive OR (X-OR) 1404. The errorcheck and correction module 1401 is coupled to the output of theserial-to-parallel converter 202 and checks the digital output of theserial-to-parallel converter 202 to determine if it is a valid digitalword. If it is not a valid digital word, then the module 1401 performsan automatic polarity flip of the digital word.

The error check and correction module 1401 includes an error check 1402at the output of the parallel-to-serial converter 202 a. The error checkmodule 1402 examines the digital word at the output of theparallel-to-serial converter 1402 and determines if it is a validdigital word within the context of the communications system 1300. Forexample, the error check module 1402 can include a RAM memory thatstores the possible digital word combinations for comparison with thedigital word output of the serial-to-parallel converter 202. If thedigital word output of the serial-to-parallel converter 202 a does notmatch any one of the possible combinations, then the digital word outputof the serial-to-parallel converter is not a valid digital word.Accordingly, one possibility is that the interface 1303 iscross-connected as discussed above. If this is so, then flipping thepolarity of the bits that make up the digital word, will convert theinvalid digital word to a valid digital word. This can be accomplishedusing an exclusive-OR gate 1404. When the error check module 1402detects an invalid digital word, then the error check module 1402 sendsa control bit logic “1” to the exclusive-OR 1404, which causes theexclusive OR to invert the digital output from the serial-to-parallelconverter, and generate a inverted digital word 1405. If the error wasintroduced by the cross-connection, then the inverted digital word 1405will be a valid digital word.

The error check module 1402 outputs a control bit “0” when it determinesthat the digital word at the output of the serial-to-parallel converteris a valid digital word. A control bit “0” does not invert the digitalword, so that the digital word passes unchanged for further processing.

The error check and correction module 1401 can be implemented usingother configurations as will be understood by those skilled in the artsbased on the discussion given herein. For instance, a logic circuitother than an X-OR can be used to flip the polarity of the digital wordif it is invalid.

An advantage of implementing the automatic polarity swap is thatcross-connect errors are rectified quickly and easily, without having tore-wire or re-configure any hardware. Furthermore, the polarity swap canbe implemented on the transmit side or the receive side. However, thereceive implementation is shown in FIG. 14. The transmit implementationwill be apparent based the description related to FIG. 14.

FIG. 15 illustrates a flowchart 1500 that further describes an automaticpolarity swap according to embodiments of the present invention.

In step 1502, a serial differential signal is received. In step 1504,the serial differential signal is converted to a parallel differentialdata word.

In step 1506, the parallel differential data word is examined todetermined if it is a valid data word for the correspondingcommunications system. For instance, the parallel differential data wordcan be compared with valid data words that are stored in a RAM. If theparallel differential data word is valid, then it is passed unmodifiedfor further processing. For example, a valid data word can bere-serialized and transmitted to a destination switch or MAC.

In step 1508, the parallel differential data word is inverted if theparallel differential data word is found to be invalid in step 1506. Forinstance, a logic circuit (such as the X-OR 1404) can be used to invertthe parallel data word is if it is invalid.

In step 1510, the inverted parallel data word can be re-examined todetermine if it is now a valid data word, and if so the invertedparallel data word can be further processed. For example, the invertedparallel data word can be serialized and retransmitted to a destinationswitch, or MAC.

Automatic Fail Switchover

FIG. 16 illustrates a system 1600 utilizing automatic fail switchoveraccording to an embodiment of the present invention. System 1600includes switches 1602 a-b, transceivers 1604 a-b, and channels 1612a-b. In the embodiment of FIG. 16, switches 1602 a-b communicate witheach other via channel 1612 a or channel 1612 b. Transceivers 1604 a-bdetermine which channel 1612 a or 1612 b switches 1602 a-b use tocommunicate.

In the following discussion, elements of system 1600 may be referred togenerally with a reference number only (i.e., without a referenceletter). For example, the discussion may refer to “transceiver 1604” ifthe discussion is similarly applicable to both transceiver 1604 a andtransceiver 1604 b. However, referring to an element using both areference number and a reference letter (e.g., transceiver 1604 a) doesnot suggest that the discussion is not applicable to another element(e.g., transceiver 1604 b) of system 1600.

Referring to FIG. 16, each transceiver 1604 includes configuration logic418 and two ports 1608 for illustrative purposes. Transceivers 1604 a-bcan include any number of ports 1608. A port 1608 can be one or moreserial ports 104 or one or more parallel ports 102, as described abovewith reference to FIG. 1. Configuration logic 418 is depicted as aswitch in FIG. 16 for illustrative purposes. The switch has a firstterminal 1614 and a second terminal 1616. When the switches intransceivers 1604 a-b are coupled to first terminals 1614 a-b,respectively, data flows between port 1608 a of transceiver 1604 a andport 1608 c of transceiver 1604 b via channel 1612 a. When the switchesare coupled to second terminals 1616 a-b, respectively, data flowsbetween ports 1608 b and 1608 d via channel 1612 b.

According to an embodiment, communications between switches 1602 a-b aremonitored for a failure. A failure can be based on non-responsiveness ofa channel, a local or remote fault, the number of illegal code wordsdetected, frequency variation exceeding a threshold, the number ofpackets transferred per unit of time falling below a threshold, etc.

Automatic fail switchover allows communications to be automaticallyswitched from one channel 1612 a or 1612 b of system 1600 to anotherchannel 1612 b or 1612 a of system 1600 upon detection of a failure.Automatic fail switchover is performed automatically by system 1600, sothat an external signal is not needed.

Failure monitoring and/or detection may be performed using hardware,software, firmware, or any combination thereof. For example, a BERT cangenerate and process test packet data to determine whether data is beingproperly transferred via a channel 1612 a or 1612 b. If the BERTdetermines that a failure has occurred with respect to a particularchannel 1612 a or 1612 b, then communications assigned to that channel1612 a or 1612 b are re-assigned to another channel 1612 b or 1612 a ofsystem 1600. In an embodiment, failure monitoring and/or detection isperformed at a PHY layer of system 1600.

A channel 1612 a or 1612 b for which a failure is detected may bedisabled, though the scope of the invention is not limited in thisrespect. For instance, the driver associated with that channel 1612 a or1612 b may be deactivated.

FIG. 17 illustrates system 1600 according to another embodiment of thepresent invention. In FIG. 17, each transceiver 1604 includesconfiguration logic 418, transmitters 1702 and 1706, and receivers 1704and 1708. Configuration logic 418 enables data to be passed to a XGMIIbus 1710 from receiver 1704 or 1708, depending on the status of at leastone of the channels 1612 a-b. For instance, if a failure is detectedwith respect to channel 1612 a, then configuration logic 418 disablesreceiver 1704 and enables receiver 1708. If a failure is detected withrespect to channel 1612 b, then configuration logic 418 disablesreceiver 1708 and enables receiver 1704.

Referring to FIG. 18, configuration logic 418 a selects receiver 1704 a,and configuration logic 418 b selects receiver 1704 b. Receivers 1704a-b are activated, and receivers 1708 a-b are deactivated. In theembodiment of FIG. 18, transceivers 1604 a and 1604 b are bothconfigured to receive data via channel 1612 a.

Referring to FIG. 19, configuration logic 418 a selects receiver 1708 a,and configuration logic 418 b selects receiver 1708 b. Receivers 1708a-b are activated, and receivers 1704 a-b are deactivated. In theembodiment of FIG. 19, transceivers 1604 a and 1604 b are bothconfigured to receive data via channel 1612 b.

Referring to FIG. 20, configuration logic 418 a selects receiver 1704 a,and configuration logic 418 b selects receiver 1708 b. Receivers 1704 aand 1708 b are activated, and receivers 1704 b and 1708 a aredeactivated. In the embodiment of FIG. 20, transceiver 1604 a isconfigured to receive data via channel 1612 a, and transceiver 1604 b isconfigured to receive data via channel 1612 b.

In FIG. 21, configuration logic 418 a selects receiver 1708 a, andconfiguration logic 418 b selects receiver 1704 b. Receivers 1708 a and1704 b are activated, and receivers 1708 b and 1704 a are deactivated.In the embodiment of FIG. 21, transceiver 1604 a is configured toreceive data via channel 1612 b, and transceiver 1604 b is configured toreceive data via channel 1612 a.

In FIGS. 17-21, data is transmitted in parallel by transmitters 1702 and1706 via channels 1612 a-b, respectively. According to an embodiment,the data is immediately available upon switchover by configuration logic418. In the embodiment of FIG. 22, configuration logic 418 furtherenables data to be passed from a XGMII bus 1710 to transmitter 1702 or1706, depending on the status of at least one of the channels 1612 a-b.

If configuration logic 418 c detects a failure with respect to channel1612 a, then configuration logic 418 c disables transmitter 1702 a andenables transmitter 1706 a. If configuration logic 418 d detects afailure with respect to channel 1612 a, then configuration logic 418 ddisables transmitter 1702 b and enables transmitter 1706 b. Ifconfiguration logic 418 c detects a failure with respect to channel 1612b, then configuration logic 418 c disables transmitter 1706 a andenables transmitter 1702 a. If configuration logic 418 d detects afailure with respect to channel 1612 b, then configuration logic 418 ddisables transmitter 1706 b and enables transmitter 1702 b.

According to an embodiment, configuration logic 418 a or 418 b is setbased on a setting of configuration logic 418 d or 418 c, respectively.In another embodiment, configuration logic 418 c or 418 d is set basedon a setting of configuration logic 418 b or 418 a, respectively.

FIG. 23 is a flow chart 2300 of a method of performing automatic failswitchover according to an embodiment of the present invention. Theinvention, however, is not limited to the description provided by theflowchart 2300. Rather, it will be apparent to persons skilled in therelevant art(s) from the teachings provided herein that other functionalflows are within the scope and spirit of the present invention.

Flowchart 2300 will be described with continued reference to transceiver1604 described above in reference to FIGS. 16-22, though the method isnot limited to those embodiments.

Referring now to FIG. 23, configuration logic 418 in a transceiver 1604determines whether a port 1608 of the transceiver 1604 is active, asshown in decision block 2310. According to an embodiment, the port 1608is active if the data is being transmitted at the port 1608. In anotherembodiment, the port 1608 is active if the data is being received at theport 1608. If the port 1608 is not active, transceiver 1604 continues tocheck whether the port 1608 is active. Otherwise, configuration logic418 determines whether certain conditions have been enabled for testing.The conditions may be predetermined, though the scope of the inventionis not limited in this respect.

In the embodiment of FIG. 23, three conditions are available for testingthe port 1608: an error condition, a byte alignment condition, and alane alignment condition. However, the scope of the invention is notlimited to the example conditions shown in FIG. 23. Any of a variety ofconditions may be tested with respect to the port 1608. As shown in FIG.23, the conditions may be checked/tested in parallel. In an embodiment,one or more conditions are checked/tested in series.

Referring to FIG. 23, configuration logic 418 determines whether theerror condition is enabled at decision block 2320. If the errorcondition is not enabled, configuration logic 418 continues to checkwhether the error condition is enabled at decision block 2320. If theerror condition is enabled, configuration logic 418 proceeds to performthe test associated with the error condition. More specifically,configuration logic 418 determines whether an error associated with theport 1608 exceeds a limit at decision block 2330. If the error does notexceed the limit, configuration logic 418 continues to check whether theerror exceeds the limit at decision block 2330. If the error exceeds thelimit, configuration logic 418 detects a failure associated with theport 1608 and switches from the port 1608 to another port at block 2380.

Configuration logic 418 determines whether the byte alignment conditionis enabled at decision block 2340. If the byte alignment condition isnot enabled, configuration logic 418 continues to check whether the bytealignment condition is enabled at decision block 2340. If the bytealignment condition is enabled, configuration logic 418 proceeds todetermine whether a byte alignment is missing at decision block 2350.According to an embodiment, byte alignment is indicated by a commacharacter, //K//, which will be familiar to persons skilled in theart(s). The comma character is included periodically within a datastream, such as once every ten bits. If the comma character is notdetected as expected within the data stream, the byte alignment is saidto be missing. If the byte alignment is not missing, configuration logic418 continues to check whether the byte alignment is missing at decisionblock 2350. If the error exceeds the limit, configuration logic 418detects a failure associated with the port 1608 and switches from theport 1608 to another port at block 2380.

Configuration logic 418 determines whether the lane alignment conditionis enabled at decision block 2360. If the lane alignment condition isnot enabled, configuration logic 418 continues to check whether the lanealignment condition is enabled at decision block 2360. If the lanealignment condition is enabled, configuration logic 418 proceeds todetermine whether a lane alignment is missing at decision block 2370. Ifthe lane alignment is not missing, configuration logic 418 continues tocheck whether the lane alignment is missing at decision block 2370. Ifthe lane alignment is missing, configuration logic 418 detects a failureassociated with the port 1608 and switches from the port 1608 to anotherport at block 2380.

According to an embodiment, one or more conditions are programmable. Forinstance, different users of transceiver 1604 may have differenttolerances with respect to a condition. In an embodiment, the limitdescribed with reference to decision block 2330 is programmable, suchthat transceiver 1604 switches from the port 1608 to another port inresponse to the number of errors exceeding X, where X is programmableusing software, hardware, firmware, or a combination thereof. In anotherembodiment, the degree of misalignment at decision block 2350 or 2370that causes an automatic fail switchover is programmable.

In an embodiment, transceiver 1604 includes registers to storeinformation associated with the conditions to be tested. Programmableand/or non-programmable values can be stored in the registers. Forexample, the registers can store information indicating whether acondition is enabled and/or satisfied.

According to an embodiment, configuration logic 418 performs the methoddescribed with reference to FIG. 23 for each port 1608 associated withconfiguration logic 418. For example, configuration logic 418 a canperform the steps of the method with respect to each of ports 1608 a and1608 a. Configuration logic 418 b can perform the steps of the methodwith respect to each of ports 1608 c and 1608 d.

Conclusion

Example embodiments of the methods, systems, and components of thepresent invention have been described herein. As noted elsewhere, theseexample embodiments have been described for illustrative purposes only,and are not limiting. Other embodiments are possible and are covered bythe invention. Such other embodiments will be apparent to personsskilled in the relevant art(s) based on the teachings contained herein.Thus, the breadth and scope of the present invention should not belimited by any of the above-described exemplary embodiments, but shouldbe defined only in accordance with the following claims and theirequivalents.

1. A transceiver, comprising: a first port configured to transmit and toreceive data over a first plurality of parallel lanes; a second portconfigured to transmit and to receive the data, over a second pluralityof parallel lanes; and a switch selectively coupled to the first portand the second port; wherein the switch is configured to activate thesecond port and to deactivate the first port when at least one of: (i)the data at a first lane from among the first plurality of parallellanes is misaligned, (ii) a number of errors at a second lane from amongthe first plurality of parallel lanes exceeds a threshold, or (iii) thedata at a third lane from among the first plurality of parallel lanes ismisaligned with the data at other lanes from among the first pluralityof parallel lanes, and wherein the switch is further configured to beginits determination of whether the data at the first lane is misalignedsubstantially simultaneously with its determination of whether thenumber of errors at the second lane exceeds the threshold and itsdetermination of whether the data at the third lane is misaligned withthe data at the other lanes.
 2. The transceiver of claim 1, wherein thethreshold is programmable.
 3. The transceiver of claim 1, wherein afailure associated with the first port is indicated when the number oferrors at the second lane exceeds the threshold.
 4. The transceiver ofclaim 1, wherein the switch is configured to enable the data to be readat the second port and to disable the data from being read at the firstport.
 5. The transceiver of claim 1, wherein the switch is configured toenable the data to be transmitted at the second port and to disable thedata from being transmitted at the first port.
 6. The transceiver ofclaim 1, further comprising: a packet bit error rate tester (BERT)configured to determine the number of errors at the second lane.
 7. Thetransceiver of claim 1, wherein the switch is configured to electricallycouple a third port to the first port or the second port.
 8. Thetransceiver of claim 7, wherein the third port is a parallel port. 9.The transceiver of claim 7, further comprising: a bus connecting thefirst port, the second port, and the third port; wherein the bus, thefirst port, the second port, and the third port are on a commonsubstrate.
 10. The transceiver of claim 9, wherein the bus is configuredto have a ring shape.
 11. The transceiver of claim 1, wherein the switchis configured to determine the data at the first lane is misaligned bydetecting a byte alignment character in an unexpected location withinthe data at the first lane, the byte alignment character beingperiodically included within the data at one or more expected locations.12. The transceiver of claim 11, wherein the byte alignment charactercomprises: a comma character.
 13. The transceiver of claim 12, whereinthe switch is configured to determine whether the data at the first laneis misaligned in parallel with determining whether the number of errorsat the second lane exceeds the threshold and whether the data at thethird lane is misaligned with the data at the other lanes.
 14. Thetransceiver of claim 1, wherein at least two of the first, the second,and the third lanes are different lanes from among the first pluralityof parallel lanes.
 15. The transceiver of claim 1, wherein the first,the second, and the third lanes represent a single lane from among thefirst plurality of parallel lanes.
 16. The transceiver of claim 1,wherein at least one of the first port or the second port is a serialport.
 17. The transceiver of claim 1, wherein at least one of the firstport or the second port is a parallel port.
 18. A method of performingautomatic fail switchover in a transceiver having a first port and asecond port, comprising: configuring the first port to be active;beginning a determination of whether the data at a first lane from amonga plurality of parallel lanes that are associated with the first port ismisaligned substantially simultaneously with a determination of whethera number of errors at a second lane from among the plurality of parallellanes exceeds a threshold and a determination of whether the data at athird lane from among the plurality of parallel lanes is misaligned withthe data at other lanes from among the plurality of parallel lanes; andactivating the second port and deactivating the first port when the dataat the first lane is misaligned, the number of errors at the second laneexceeds the threshold, or the data at the third lane is misaligned withthe data at the other lanes.
 19. The method of claim 18, whereinactivating the second port comprises: enabling the data to betransmitted at the second port, and wherein deactivating the first portcomprises: disabling the data from being transmitted at the first port.20. The method of claim 18, wherein activating the second portcomprises: enabling the data to be read at the second port, and whereindeactivating the first port comprises: disabling the data from beingread at the first port.
 21. The method of claim 18, wherein the step ofdetermining whether the data at the first lane is misaligned comprises:detecting a byte alignment character in an unexpected location withinthe data at the first lane, the byte alignment character beingperiodically included within the data at the first lane at one or moreexpected locations.
 22. The method of claim 21, wherein the bytealignment character comprises: a comma character.
 23. The method ofclaim 18, wherein at least two of the first, the second, and the thirdlanes are different lanes from among the first plurality of parallellanes.
 24. The method of claim 18, wherein the first, the second, andthe third lanes represent a single lane from among the first pluralityof parallel lanes.
 25. The method of claim 18, wherein at least one ofthe first port or the second port is a serial port.
 26. The method ofclaim 18, wherein at least one of the first port or the second port is aparallel port.
 27. The method of claim 18, further comprising:determining whether the data at the first lane is misaligned in parallelwith determining whether the number of errors at the second lane exceedsthe threshold and whether the data at the third lane is misaligned withthe data at the other lanes.
 28. A transceiver, comprising: a firstparallel port configured to transmit and to receive data over aplurality of lanes that are associated with a communication channel; anda switch selectively coupled to the first parallel port and to a secondparallel port; wherein the switch is configured to activate the secondparallel port and to deactivate the first parallel port when at leastone of: (i) the data at a lane from among the plurality of lanes ismisaligned, (ii) a number of errors at the lane exceeds a threshold, or(iii) the data at the lane is misaligned with the data at other lanesfrom among the plurality of lanes, wherein the switch is furtherconfigured to begin its determination of whether the data at the lane ismisaligned substantially simultaneously with its determination ofwhether the number of errors at the lane exceeds the threshold and itsdetermination of whether the data at the lane is misaligned with thedata at the other lanes.
 29. The transceiver of claim 28, wherein theswitch electrically couples a third parallel port to the first parallelport or the second parallel port.
 30. The transceiver of claim 29,further comprising: a bus connecting the first parallel port, the secondparallel port, and the third parallel port; wherein the bus, the firstparallel port, the second parallel port, and the third parallel port areon a common substrate.
 31. The transceiver of claim 28, wherein theswitch, is configured to determine whether the data at the lane ismisaligned in parallel with determining whether the number of errors atthe lane and whether the data at the lane is misaligned with the data atthe other lanes.
 32. The transceiver of claim 28, wherein the switch isfurther configured to begin its determination of whether the data at thelane is misaligned substantially simultaneously with its determinationof whether the number of errors at the lane exceeds the threshold andits determination of whether the data at the lane is misaligned with thedata at the other lanes.
 33. The transceiver of claim 28, wherein atleast two of the first, the second, and the third lanes are differentlanes from among the plurality of lanes.
 34. The transceiver of claim28, wherein the first, the second, and the third lanes represent asingle lane from among the plurality of lanes.